PCIe 8 draft races ahead, final spec still on track for 2028

The v0.5 eighth generation Peripheral Component Interconnect Express (PCIe) standard document has been released ahead of schedule, but the full spec delivery by 2028 remains on track.

PCIe interconnects are used to link fast peripheral devices to a host system. PCIe gen 4 and 5 devices, such as SSDs, are shipping now, with PCIe gen 6 devices in development. The PCIe gen 7 spec is available, and the PCIe gen 8 spec is in development.

Computers of all types – x86, GPUs, Arm, and RISC-V – are getting faster as IT workloads increase in complexity and users demand results in shorter timescales. These speed increases mean compute engines need to be fed with data faster, and need to output data faster as well. That means the peripheral devices need to accelerate their operations and the link to those devices – the peripheral interconnect – has to step up its speed to match.

PCIe is used to link CPUs to GPUs, but GPUs are now so fast that dedicated links are used to interconnect them, such as Nvidia's NVLink. PCIe is the dominant interconnect standard in the x86 CPU world and needs to match increases in CPU performance across generations.

Each PCIe generation doubles the speed of the preceding generation to be able to cope with the increased amount of data flowing through a computing system.

A PCIe link has parallel lanes and the link bandwidth per lane increases with each generation. PCIe 8.0 lanes are expected to operate at 256 GT/s, double PCIe 7.0's 128 GT/s. A chart shows the dramatic effects of the generational speed doubling:

v0.5 is the official first draft of the spec, incorporating all the feedback received from PCI-SIG members after the release of draft 0.3 in September 2025. The SIG says the goal of the PCIe 8.0 specification is to deliver the high bandwidth and low latency needed for data-intensive markets including AI, datacenters, high-speed networking, edge computing, quantum computing, and more.

The gen 8 objectives are:

• Delivering 256.0 GT/s raw bit rate and up to 1.0 TB/s bi-directionally via x16 configuration
• Evaluating new connector technology
• Ensuring latency, FEC and reliability targets are achieved
• Maintaining backward compatibility with previous generations of PCIe technology
• Improving bandwidth through protocol enhancements
• Reducing power through additional techniques

We can expect PCIe gen 8 devices to appear from 2030 onward. There is already informal discussion of a PCIe gen 9 spec, ahead of official development, which we would expect to double the transfer speed again to 512 GT/s per lane and appear as a spec document in 2031. Optical technology will likely have an important role.

PCI-SIG has more than 1,000 members, reflecting how pervasive the interconnect has become. They can access the PCIe 8.0 specification, draft 0.5 on the members workspace on Causeway. Other interested parties can join the PCI-SIG here.