Panmnesia's two unification efforts; PCIe/CXL and UAL/Ethernet

Fabless, semiconductor company Panmnesia has a funded project to develop controllers and switches supporting UALink and Ethernet, and it will sample ship its combined PCIe 6.4-CXL 3.2 fusion switch chip in the second half of this year. 

Panmnesia CEO Dr Myoungsoo Jung outlined CXL and UALInk/NVLink fusion ideas last July. He described a CXL-over-XLink architecture. The Fusion chip supports PCIe and CXL protocols on a single die, but not UALink.

The Fusion  chip’s internal controller achieves double-digit nanosecond latency; Panmnesia saying it boosts response time and throughput across the switch and overall system. The controller logic can also be modified to accommodate customer-specific requirements, enabling expansion into tailored custom systems.

The PCIe/CXL switch supports both port-based routing (PBR) and hierarchy-based routing (HBR) on a single chip. It says HBR limits connectivity to a tree structure centered on the CPU, while PBR allows switches and devices to be freely interconnected in any topology. Multiple switches can be chained together to connect thousands of devices across multiple server racks into a single fabric, without relying on high-latency networks such as Ethernet.

The switch chip enables Direct Peer-to-Peer communication on a fabric built with port-based routing, allowing devices to exchange data directly with minimal CPU involvement and maximizing communication efficiency. Panmnesia says it’s currently the only company in the industry to offer a switch chip with port-based routing support.

The company reckons its PCIe 6.4-CXL 3.2 fusion switch enables composable architecture to be implemented at rack scale, saying:”This translates into reduced capital expenditure (CAPEX) and operating expenditure (OPEX) for systems handling large-scale workloads, including large language models (LLMs), retrieval-augmented generation (RAG), deep learning recommendation models (DLRM), and MPI-based scientific simulations.”

UALink and Ethernet

UAL (Ultra Accelerator Link) is an alternative to Nvidia’s NVLink and designed to enable high-speed connectivity between AI accelerators regardless of manufacturer. A UALink supporting group consists of AMD, AWS, Google, Microsoft, and Meta, along with Panmnesia and many others.

Ethernet-based accelerator linking technologies are also being proposed and developed by, for example, ESUN (Ethernet for Scale-up Networking), led by the Open Compute Project (OCP). Panmnesia is an active member of OCP.

Panmnesia has secured around $10 million in funding for its UAL/Ethernet project and will develop controllers and switches supporting UALink and Ethernet-based protocols. A switch SoC supporting protocols such as UALink is expected to be available from the second half of 2027.

Could we envisage a super-Fusion chip, one that brings PCIe, CXL, UALInk and Ethernet together? We could view this as a logical evolution of Panmnesia’s roadmap, and the AI infrastructure market’s push toward unified, open, low-latency fabrics. 

Check out the PanSwitch's PCIe and CXL specifications here.